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Sponsor: CEOL, International Software and Productivity Engineering Institute, Intelligent Support Ltd, Solari, Minteos, M.O.S.T., Electronic Center and Legale Fiscale
Homepage: http://digilander.libero.it/systemcfl/dtvcs
Email: ss.dtvcs@gmail.com
Organizers: DTVCS and IASTED
Deadline for abstracts: April 01, 2008
Description:
The main target of the Special Session DTVCS in the IASTED International Conference on Circuits and Systems (CS 2008) is to bring together engineering researchers, computer scientists, practitioners and people from industry to exchange theories, ideas, techniques and experiences related to the areas of design, testing and formal verification techniques for integrated circuits and systems. Contributions on UML and formal paradigms based on process algebras, Petri-nets, automaton theory and BDDs in the context of design, testing and formal verification techniques for integrated circuits and systems are also encouraged.
Topics of interest include, but are not limited to, the following: digital, analog, mixed-signal and RF test, built-in self test, ATPG, theory and foundations: model checking, SAT-based methods, use of PSL, compositional methods and probabilistic methods, applications of formal methods: equivalence checking, CSP applications and transaction-level verification, verification through hybrid techniques, verification methods based on hardware description/system-level languages (e.g. VHDL, SystemVerilog and SystemC), testing and verification applications: tools, industrial experience reports and case studies
Please visit the web-site of DTVCS 2008 (http://digilander.libero.it/systemcfl/dtvcs) for further information on the hosting conference, industrial collaborators, technical program committee, submission guidelines, deadlines, proceedings and publications.
Submitted by: Ka Lok Man
Date received: February 10, 2008, revised February 11, 2008
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